Thanks, MarisaNiederhauser, ThomasHaeberlin, AndreasWildhaber, RetoVogel, RolfGoette, JosefJacomet, Marcel2024-08-132024-08-1320171932-45451940-999010.1109/tbcas.2016.2619858https://irf.fhnw.ch/handle/11654/46784A new pseudo asynchronous level crossing analogue-to-digital converter (ADC) architecture targeted for low-power, implantable, long-term biomedical sensing applications is presented. In contrast to most of the existing asynchronous level crossing ADC designs, the proposed design has no digital-to-analogue converter (DAC) and no continuous time comparators. Instead, the proposed architecture uses an analogue memory cell and dynamic comparators. The architecture retains the signal activity dependent sampling operation by generating events only when the input signal is changing. The architecture offers the advantages of smaller chip area, energy saving and fewer analogue system components. Beside lower energy consumption the use of dynamic comparators results in a more robust performance in noise conditions. Moreover, dynamic comparators make interfacing the asynchronous level crossing system to synchronous processing blocks simpler. The proposed ADC was implemented in 0.35 μm complementary metal-oxide-semiconductor (CMOS) technology, the hardware occupies a chip area of 0.0372 mm 2 and operates from a supply voltage of 1.8 V to 2.4 V. The ADC's power consumption is as low as 0.6 μW with signal bandwidth from 0.05 Hz to 1 kHz and achieves an equivalent number of bits (ENOB) of up to 8 bits.enanalogue memory cellanalogue-to-digital conversion (ADC)asynchronous level crossing ADCdynamic compara torECG recordinglevel crossing500 - Naturwissenschaften und Mathematik01A - Beitrag in wissenschaftlicher Zeitschrift267-278