Influence of post-metallization annealing time on the electrical response of AINx-based MOS capacitor on 4H-SiC substrate

Abstract

This work investigates the structural and electrical properties of an AI/AINx /passivation layer/4H-SiC/AI MOS capacitor subjected to forming gas annealing. The dielectric stack was characterized using ellipsometry, AFM, Raman spectroscopy, and FTIR, revealing a non-stoichiometric AINx film with predominantly amorphous structure and evidence of AI-rich composition. Electrical characterization was performed through high-frequency (100 kHz) C–V measurements in both forward and reverse sweeps. The as-deposited device exhibited a pronounced hysteresis (ΔVFB=1.40 V) and a wide voltage window, indicating a high density of trapped charges and interface states. After cumulative annealing at 450 °C, the voltage window was significantly reduced and the hysteresis decreased to a minimum of 0.16 V after 20 minutes, indicating improved interface quality. The interface state density (Dit ) was estimated using a simplified Terman-based approach, showing a reduction from ∼1013cm−2eV−1 to ∼1012cm−2eV−1 after annealing. These results demonstrate that the combination of an AINx dielectric layer and optimized annealing effectively improves the electrical performance of SiC MOS structures.