Subthreshold logic for low-area and energy efficient true random number generator
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Author (Corporation)
Publication date
07.06.2018
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Type
04B - Conference paper
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Parent work
Proceedings for 2018 IEEE COOL Chips 21
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Pages / Duration
1-3
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IEEE
Place of publication / Event location
Yokohama
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Abstract
This paper discusses the advantages of subthreshold logic for True Random Number Generators (TRNG). In this work, the entropy is modeled, and a lower bound of Shannon's entropy per output bit can quickly be estimated. Thanks to this model, sizing TRNGs in subthreshold logic is quite simple and defining design guidelines for low-energy and low-area TRNGs is straightforward. A TRNG in 180nm CMOS technology has been designed, demonstrating low complexity (305 gates) and energy efficacy (30pJ/bit) at 0.5 Kbit/s.
Keywords
Entropy, Jitter, Generators, Cryptography, Logic gates, Ring oscillators, Applied Cryptography, Random Numbers Generators, Asynchronous Circuits, Subthreshold Logic
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Event
2018 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS)
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ISBN
978-1-5386-6103-1
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Language
English
Created during FHNW affiliation
No
Strategic action fields FHNW
Publication status
Published
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Peer review of the complete publication
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Closed
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Citation
Coustans, M., Cherkaoui, A., Fesquet, L., Terrier, C., Salgado, S., Eberhardt, T., & Kayal, M. (2018). Subthreshold logic for low-area and energy efficient true random number generator. Proceedings for 2018 IEEE COOL Chips 21, 1–3. https://doi.org/10.1109/CoolChips.2018.8373081