Low Power Sampling Latch for up to 25\,Gb/s 2x Oversampling CDR in 90\mbox-nm CMOS
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2006
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04B - Conference paper
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Proc. ESSCIRC
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106-109
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Montreux
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von Bueren, G., Rodoni, L., Kormer, C., Jäckel, H., Huber, A., & Morf, T. (2006). Low Power Sampling Latch for up to 25\,Gb/s 2x Oversampling CDR in 90\mbox-nm CMOS. Proc. ESSCIRC, 106–109. http://hdl.handle.net/11654/17731