Institut für Medizintechnik und Medizininformatik
Dauerhafte URI für die Sammlunghttps://irf.fhnw.ch/handle/11654/23
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Ergebnisse nach Hochschule und Institut
Publikation Bufferless compression of asynchronously sampled ECG signals in cubic hermitian vector space(IEEE, 2015) Thanks, Marisa; Niederhauser, Thomas; Haeberlin, Andreas; Wildhaber, Reto; Vogel, Rolf; Jacomet, Marcel; Goette, JosefAsynchronous level crossing sampling analog-to-digital converters (ADCs) are known to be more energy efficient and produce fewer samples than their equidistantly sampling counterparts. However, as the required threshold voltage is lowered, the number of samples and, in turn, the data rate and the energy consumed by the overall system increases. In this paper, we present a cubic Hermitian vector-based technique for online compression of asynchronously sampled electrocardiogram signals. The proposed method is computationally efficient data compression. The algorithm has complexity O(n), thus well suited for asynchronous ADCs. Our algorithm requires no data buffering, maintaining the energy advantage of asynchronous ADCs. The proposed method of compression has a compression ratio of up to 90% with achievable percentage root-mean-square difference ratios as a low as 0.97. The algorithm preserves the superior feature-to-feature timing accuracy of asynchronously sampled signals. These advantages are achieved in a computationally efficient manner since algorithm boundary parameters for the signals are extracted a priori.01A - Beitrag in wissenschaftlicher ZeitschriftPublikation Pseudo asynchronous level crossing ADC for ECG signal acquisition(IEEE, 2017) Thanks, Marisa; Niederhauser, Thomas; Haeberlin, Andreas; Wildhaber, Reto; Vogel, Rolf; Goette, Josef; Jacomet, MarcelA new pseudo asynchronous level crossing analogue-to-digital converter (ADC) architecture targeted for low-power, implantable, long-term biomedical sensing applications is presented. In contrast to most of the existing asynchronous level crossing ADC designs, the proposed design has no digital-to-analogue converter (DAC) and no continuous time comparators. Instead, the proposed architecture uses an analogue memory cell and dynamic comparators. The architecture retains the signal activity dependent sampling operation by generating events only when the input signal is changing. The architecture offers the advantages of smaller chip area, energy saving and fewer analogue system components. Beside lower energy consumption the use of dynamic comparators results in a more robust performance in noise conditions. Moreover, dynamic comparators make interfacing the asynchronous level crossing system to synchronous processing blocks simpler. The proposed ADC was implemented in 0.35 μm complementary metal-oxide-semiconductor (CMOS) technology, the hardware occupies a chip area of 0.0372 mm 2 and operates from a supply voltage of 1.8 V to 2.4 V. The ADC's power consumption is as low as 0.6 μW with signal bandwidth from 0.05 Hz to 1 kHz and achieves an equivalent number of bits (ENOB) of up to 8 bits.01A - Beitrag in wissenschaftlicher Zeitschrift