Hardware acceleration of digital filters using the STM32 FMAC peripheral - a performance comparison
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Publication date
10.2026
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Collections
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05 - Report
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Hochschule für Technik und Umwelt FHNW
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Windisch
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Abstract
Filters are a fundamental component of signal processing, and an increasing number of them are implemented digitally. While digital implementations offer increased flexibility they simultaneously set higher demands on microcontrollers. As a result selected generations of recent STM32 microcontrollers ship with a Filter Math Accelerator (FMAC) peripheral which allows to offload the filtering from the CPU. This letter provides a performance and accuracy comparison of the FMAC peripheral in single section and second order sections configuration to the widely adopted CMSIS-DSP software implementation. The results show that depending on configuration, filter order and data type the FMAC reduces CPU usage up to 99% - at the cost of accuracy - thus making it ideal for applications where concurrent tasks have to be executed.
Keywords
Signalprocessing, hardware acceleration, Filtering, Filter Math Accelerator (FMAC), STM32
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English
Created during FHNW affiliation
Yes
Strategic action fields FHNW
Zero Emission
Publication status
Unpublished
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not peer-reviewed
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Citation
Hochuli, M., & Gorenflo, S. (2026). Hardware acceleration of digital filters using the STM32 FMAC peripheral - a performance comparison. Hochschule für Technik und Umwelt FHNW. https://doi.org/10.26041/fhnw-17407