Low Power Sampling Latch for up to 25\,Gb/s 2x Oversampling CDR in 90\mbox-nm CMOS

dc.contributor.authorvon Bueren, Georg
dc.contributor.authorRodoni, Lucio
dc.contributor.authorKormer, Christian
dc.contributor.authorJäckel, Heinz
dc.contributor.authorHuber, Alexander
dc.contributor.authorMorf, Thomas
dc.date.accessioned2016-04-06T14:25:37Z
dc.date.available2016-04-06T14:25:37Z
dc.date.issued2006
dc.identifier.urihttp://hdl.handle.net/11654/17731
dc.relation.ispartofProc. ESSCIRC
dc.spatialMontreux
dc.titleLow Power Sampling Latch for up to 25\,Gb/s 2x Oversampling CDR in 90\mbox-nm CMOS
dc.type04B - Beitrag Konferenzschrift
dspace.entity.typePublication
fhnw.InventedHereYes
fhnw.affiliation.hochschuleHochschule für Technikde_CH
fhnw.affiliation.institutlnstitut für Sensorik und Elektronikde_CH
fhnw.pagination106-109
relation.isAuthorOfPublication911e2394-19ba-4b7d-b8bc-84e2a01e8e53
relation.isAuthorOfPublication.latestForDiscovery911e2394-19ba-4b7d-b8bc-84e2a01e8e53
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