Huber, Alexander
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40 Gb/s quarter rate CDR with data rate selection in 90\,nm CMOS
2010, Huber, Alexander, Schmatz, Martin, Toifl, Thomas, Menolfi, Christian, Kossel, Marcel, von Bueren, Georg, Rodoni, Lucio, Jäckel, Heinz, Morf, Thomas
A Combined Dynamic and Static Frequency Divider for a 40\,GHz PLL in 80\,nm CMOS
2006, von Bueren, Georg, Kromer, Christian, Ellinger, Frank, Huber, Alexander, Schmatz, Martin, Jäckel, Heinz
High speed InP-based HBTs and OEICs
2002, Jäckel, Heinz, Hammer, Urs, Ruiz, Javier, Schnyder, Iwan, Gaspar, A., Huber, D., Huber, Alexander, Rohner, A., Schwarz, Volker
Design and phase noise analysis of a multiphase 6 to 11 GHz PLL
2009, Bueren, George von, Barras, David, Jäckel, Heinz, Huber, Alexander, Kromer, Christian, Kossel, Marcel
Low Power Sampling Latch for up to 25\,Gb/s 2x Oversampling CDR in 90\mbox-nm CMOS
2006, von Bueren, Georg, Rodoni, Lucio, Kormer, Christian, Jäckel, Heinz, Huber, Alexander, Morf, Thomas
The Influence of the Emitter Orientation on the Noise Characteristics of InP/InGaAs(P) DHBTs
2000, Huber, Alexander, Schnyder, Iwan, Jäckel, Heinz, Bergamaschi, Crispino, Schenk, Karl
A 5.75 to 44\,Gb/s quarter rate CDR with data rate selection in 90nm bulk CMOS
2008, Rodoni, Lucio, von Buren, Georg, Huber, Alexander, Schmatz, Martin, Jäckel, Heinz
Noise model of InP-InGaAs SHBTs for RF circuit design
2002, Huber, Alexander, Huber, D., Bergamaschi, Crispino, Morf, Thomas, Jäckel, Heinz